`timescale 1ns/1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:         Beijing ICfusion technology Co.Ltd
// Website:         http://www.icfusion.com/
// Create Date:     04/20/2020
//
// Design Name:     zs
// Target Devices:  PRX100T
// Tool Versions:   Vivado18.2
//
// Module Name:     
// Project Name:    eeprom_wr_test
// Description:     
// 
// Dependencies: 
// Revision:
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////
module key_filter#(
parameter DVI_CNT = 50
)(

input			clk,			//50m
input			rst_n,

input	[7:1]	pb,

output  reg    center_flag,
output  reg    up_flag,
output  reg    down_flag,
output  reg    left_flag,
output  reg    right_flag

    );
//========================
wire			us_p;
wire			ms_p;
wire			s_p;   
 
block_dvi#(
.DVI_CNT(DVI_CNT)
) block_dvi_inst
(
	.SYS_CLK	(clk),
	.SYS_RST_N	(rst_n),
	.US_P		(us_p),  
	.MS_P		(ms_p),
	.S_P		(s_p)
);

wire	[7:1]	pb_flag;
// Generate block
genvar i;
generate
	for(i=1; i<8; i=i+1) 
	begin: BLOCK1
		pb_filter pb_filter_inst
			(
				.SYS_CLK	(clk),
				.SYS_RST_N	(rst_n),
				.MS_P		(ms_p),   
				.KEYIN		(pb[i]),  
				.KEYOUT		(pb_flag[i])
			);  
	end
endgenerate    

always @ (posedge clk)
if(!rst_n)
begin
    center_flag <= 0;
    up_flag <= 0;    
    down_flag <= 0;  
    left_flag <= 0;  
    right_flag <= 0;  
end
else
begin
    center_flag <= pb_flag[5];
    up_flag <= pb_flag[2];    
    down_flag <= pb_flag[7];  
    left_flag <= pb_flag[4];  
    right_flag <= pb_flag[6];  
end

endmodule
